1. Field of the Invention
The present invention relates to transistors in integrated circuits, including transistors suitable for use as high voltage pass transistors like those utilized in some decoding structures for high density memory.
2. Description of Related Art
In high density memory, the arrays of memory cells are often divided into a plurality of blocks of memory cells. Each block of memory cells may include local word lines, requiring corresponding local word line drivers. In these configurations, there can be a global word line driver which drives a set of global word lines for a column of blocks in the array. Each word line in the set of global word lines is set according to the operation being applied to the selected blocks, such as read, program, and erase for high density flash devices. Some operations can require high voltages and some can require negative voltages for some types of memory devices. As a result, word line drivers are required that can meet difficult high voltage and negative voltage operating parameters.
Word line drivers in these environments can include pass transistors which are used to transfer voltages from global word lines to local word lines. These pass transistors can experience high electric fields sufficient to cause unwanted charge trapping in the insulating materials over source/drain terminals. Charge trapped in these locations can create electric fields sufficient to deplete charge carriers in zones near the edges of the channels of the pass transistors. These depletion zones can increase the resistance of the pass transistor when it is operating to transfer voltages. As a result of the increased resistance, a substantial drop in voltage can occur across the device. This drop in voltage can interfere with specified operation of the decoder, and cause other problems.
Transistors utilized in other relatively high voltage environments can experience similar problems.
Thus it is desirable to provide a technology which can address problems arising because of unwanted charge trapping in high voltage transistors, and a technology for deploying such transistors in high density memory devices.